URL https://opencores.org/ocsvn/pci/pci/trunk

Subversion Repositories pci

[/] [pci/] [tags/] [rel_3/] [rtl/] [verilog/] [pci_user_constants.v] - Rev 60

Rev	Log message	Author	Age	Path
60	Added support for Virtual Silicon two port RAM. Didn't run regression on it yet!	mihad	7936d 19h	/pci/tags/rel_3/rtl/verilog/pci_user_constants.v
45	Added a few testcases. Repaired wrong reset value for PCI_AM5 register. Repaired Parity Error Detected bit setting. Changed PCI_AM0 to always enabled(regardles of PCI_AM0 define), if image 0 is used as configuration image	mihad	7985d 01h	/pci/tags/rel_3/rtl/verilog/pci_user_constants.v
33	Added some testcases, removed un-needed fifo signals	mihad	8146d 01h	/pci/tags/rel_3/rtl/verilog/pci_user_constants.v
18	* empty log message *	mihad	8177d 22h	/pci/tags/rel_3/rtl/verilog/pci_user_constants.v