URL https://opencores.org/ocsvn/pci/pci/trunk

Subversion Repositories pci

[/] [pci/] [tags/] [rel_3/] [rtl/] [verilog/] [pciw_fifo_control.v] - Rev 66

Rev	Log message	Author	Age	Path
66	Changed empty status generation in pciw_fifo_control.v	mihad	7925d 05h	/pci/tags/rel_3/rtl/verilog/pciw_fifo_control.v
59	Added meta flop module for easier meta stable FF identification during synthesis	mihad	7939d 01h	/pci/tags/rel_3/rtl/verilog/pciw_fifo_control.v
58	Removed all logic from asynchronous reset network	mihad	7944d 01h	/pci/tags/rel_3/rtl/verilog/pciw_fifo_control.v
21	Repaired a few bugs, updated specification, added test bench files and design document	mihad	8180d 02h	/pci/tags/rel_3/rtl/verilog/pciw_fifo_control.v
6	Updated all files with inclusion of timescale file for simulation purposes.	mihad	8299d 09h	/pci/tags/rel_3/rtl/verilog/pciw_fifo_control.v
2	New project directory structure	mihad	8302d 02h	/pci/tags/rel_3/rtl/verilog/pciw_fifo_control.v