URL https://opencores.org/ocsvn/pci/pci/trunk

Subversion Repositories pci

[/] [pci/] [tags/] [rel_3/] [rtl/] [verilog/] [pciw_pcir_fifos.v] - Rev 59

Rev	Log message	Author	Age	Path
59	Added meta flop module for easier meta stable FF identification during synthesis	mihad	7937d 06h	/pci/tags/rel_3/rtl/verilog/pciw_pcir_fifos.v
58	Removed all logic from asynchronous reset network	mihad	7942d 06h	/pci/tags/rel_3/rtl/verilog/pciw_pcir_fifos.v
33	Added some testcases, removed un-needed fifo signals	mihad	8146d 10h	/pci/tags/rel_3/rtl/verilog/pciw_pcir_fifos.v
21	Repaired a few bugs, updated specification, added test bench files and design document	mihad	8178d 06h	/pci/tags/rel_3/rtl/verilog/pciw_pcir_fifos.v
6	Updated all files with inclusion of timescale file for simulation purposes.	mihad	8297d 14h	/pci/tags/rel_3/rtl/verilog/pciw_pcir_fifos.v
2	New project directory structure	mihad	8300d 06h	/pci/tags/rel_3/rtl/verilog/pciw_pcir_fifos.v