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[/] [pci/] [tags/] [rel_3/] [rtl/] [verilog/] [pciw_pcir_fifos.v] - Rev 68

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Rev Log message Author Age Path
68 Changed wrong signal name scanb_sen into scanb_en. tadejm 7928d 22h /pci/tags/rel_3/rtl/verilog/pciw_pcir_fifos.v
67 Changed BIST signals for RAMs. tadejm 7929d 03h /pci/tags/rel_3/rtl/verilog/pciw_pcir_fifos.v
63 Added additional testcase and changed rst name in BIST to trst mihad 7935d 15h /pci/tags/rel_3/rtl/verilog/pciw_pcir_fifos.v
62 Added BIST signals for RAMs. mihad 7938d 08h /pci/tags/rel_3/rtl/verilog/pciw_pcir_fifos.v
59 Added meta flop module for easier meta stable FF identification during synthesis mihad 7946d 09h /pci/tags/rel_3/rtl/verilog/pciw_pcir_fifos.v
58 Removed all logic from asynchronous reset network mihad 7951d 10h /pci/tags/rel_3/rtl/verilog/pciw_pcir_fifos.v
33 Added some testcases, removed un-needed fifo signals mihad 8155d 14h /pci/tags/rel_3/rtl/verilog/pciw_pcir_fifos.v
21 Repaired a few bugs, updated specification, added test bench files and design document mihad 8187d 10h /pci/tags/rel_3/rtl/verilog/pciw_pcir_fifos.v
6 Updated all files with inclusion of timescale file for simulation purposes. mihad 8306d 17h /pci/tags/rel_3/rtl/verilog/pciw_pcir_fifos.v
2 New project directory structure mihad 8309d 10h /pci/tags/rel_3/rtl/verilog/pciw_pcir_fifos.v

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