URL https://opencores.org/ocsvn/pci/pci/trunk

Subversion Repositories pci

[/] [pci/] [tags/] [rel_3/] [rtl/] [verilog/] [pciw_pcir_fifos.v] - Rev 68

Rev	Log message	Author	Age	Path
68	Changed wrong signal name scanb_sen into scanb_en.	tadejm	7929d 00h	/pci/tags/rel_3/rtl/verilog/pciw_pcir_fifos.v
67	Changed BIST signals for RAMs.	tadejm	7929d 05h	/pci/tags/rel_3/rtl/verilog/pciw_pcir_fifos.v
63	Added additional testcase and changed rst name in BIST to trst	mihad	7935d 18h	/pci/tags/rel_3/rtl/verilog/pciw_pcir_fifos.v
62	Added BIST signals for RAMs.	mihad	7938d 11h	/pci/tags/rel_3/rtl/verilog/pciw_pcir_fifos.v
59	Added meta flop module for easier meta stable FF identification during synthesis	mihad	7946d 12h	/pci/tags/rel_3/rtl/verilog/pciw_pcir_fifos.v
58	Removed all logic from asynchronous reset network	mihad	7951d 12h	/pci/tags/rel_3/rtl/verilog/pciw_pcir_fifos.v
33	Added some testcases, removed un-needed fifo signals	mihad	8155d 16h	/pci/tags/rel_3/rtl/verilog/pciw_pcir_fifos.v
21	Repaired a few bugs, updated specification, added test bench files and design document	mihad	8187d 13h	/pci/tags/rel_3/rtl/verilog/pciw_pcir_fifos.v
6	Updated all files with inclusion of timescale file for simulation purposes.	mihad	8306d 20h	/pci/tags/rel_3/rtl/verilog/pciw_pcir_fifos.v
2	New project directory structure	mihad	8309d 12h	/pci/tags/rel_3/rtl/verilog/pciw_pcir_fifos.v