URL https://opencores.org/ocsvn/pci/pci/trunk

Subversion Repositories pci

[/] [pci/] [tags/] [rel_3/] [rtl/] [verilog/] [wb_slave_unit.v] - Rev 21

Rev	Log message	Author	Age	Path
21	Repaired a few bugs, updated specification, added test bench files and design document	mihad	8176d 04h	/pci/tags/rel_3/rtl/verilog/wb_slave_unit.v
6	Updated all files with inclusion of timescale file for simulation purposes.	mihad	8295d 12h	/pci/tags/rel_3/rtl/verilog/wb_slave_unit.v
2	New project directory structure	mihad	8298d 04h	/pci/tags/rel_3/rtl/verilog/wb_slave_unit.v