URL https://opencores.org/ocsvn/pci/pci/trunk

Subversion Repositories pci

[/] [pci/] [tags/] [rel_3/] [rtl/] [verilog/] [wb_slave_unit.v] - Rev 68

Rev	Log message	Author	Age	Path
68	Changed wrong signal name scanb_sen into scanb_en.	tadejm	7917d 16h	/pci/tags/rel_3/rtl/verilog/wb_slave_unit.v
67	Changed BIST signals for RAMs.	tadejm	7917d 21h	/pci/tags/rel_3/rtl/verilog/wb_slave_unit.v
63	Added additional testcase and changed rst name in BIST to trst	mihad	7924d 10h	/pci/tags/rel_3/rtl/verilog/wb_slave_unit.v
62	Added BIST signals for RAMs.	mihad	7927d 02h	/pci/tags/rel_3/rtl/verilog/wb_slave_unit.v
58	Removed all logic from asynchronous reset network	mihad	7940d 04h	/pci/tags/rel_3/rtl/verilog/wb_slave_unit.v
21	Repaired a few bugs, updated specification, added test bench files and design document	mihad	8176d 04h	/pci/tags/rel_3/rtl/verilog/wb_slave_unit.v
6	Updated all files with inclusion of timescale file for simulation purposes.	mihad	8295d 11h	/pci/tags/rel_3/rtl/verilog/wb_slave_unit.v
2	New project directory structure	mihad	8298d 04h	/pci/tags/rel_3/rtl/verilog/wb_slave_unit.v