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[/] [pci/] [tags/] [rel_3/] [rtl/] [verilog/] [wb_tpram.v] - Rev 68

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Rev Log message Author Age Path
68 Changed wrong signal name scanb_sen into scanb_en. tadejm 7932d 22h /pci/tags/rel_3/rtl/verilog/wb_tpram.v
67 Changed BIST signals for RAMs. tadejm 7933d 03h /pci/tags/rel_3/rtl/verilog/wb_tpram.v
63 Added additional testcase and changed rst name in BIST to trst mihad 7939d 16h /pci/tags/rel_3/rtl/verilog/wb_tpram.v
62 Added BIST signals for RAMs. mihad 7942d 08h /pci/tags/rel_3/rtl/verilog/wb_tpram.v
60 Added support for Virtual Silicon two port RAM. Didn't run regression on it yet! mihad 7950d 08h /pci/tags/rel_3/rtl/verilog/wb_tpram.v
49 Extracted distributed RAM module from wb/pci_tpram.v to its own file, got rid of undef directives mihad 7992d 09h /pci/tags/rel_3/rtl/verilog/wb_tpram.v
18 *** empty log message *** mihad 8191d 11h /pci/tags/rel_3/rtl/verilog/wb_tpram.v

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