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[/] [pci/] [tags/] [rel_3/] [rtl/] [verilog/] [wbr_fifo_control.v] - Rev 71

Rev	Log message	Author	Age	Path
71	Changed the code a bit to make it more readable. Functionality not changed in any way. More robust synchronization in fifos is still pending.	mihad	7880d 15h	/pci/tags/rel_3/rtl/verilog/wbr_fifo_control.v
59	Added meta flop module for easier meta stable FF identification during synthesis	mihad	7938d 19h	/pci/tags/rel_3/rtl/verilog/wbr_fifo_control.v
58	Removed all logic from asynchronous reset network	mihad	7943d 19h	/pci/tags/rel_3/rtl/verilog/wbr_fifo_control.v
21	Repaired a few bugs, updated specification, added test bench files and design document	mihad	8179d 20h	/pci/tags/rel_3/rtl/verilog/wbr_fifo_control.v
6	Updated all files with inclusion of timescale file for simulation purposes.	mihad	8299d 03h	/pci/tags/rel_3/rtl/verilog/wbr_fifo_control.v
2	New project directory structure	mihad	8301d 20h	/pci/tags/rel_3/rtl/verilog/wbr_fifo_control.v