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Subversion Repositories pci

[/] [pci/] [tags/] [rel_3/] [rtl/] [verilog/] [wbw_wbr_fifos.v] - Rev 63

Rev	Log message	Author	Age	Path
63	Added additional testcase and changed rst name in BIST to trst	mihad	7939d 14h	/pci/tags/rel_3/rtl/verilog/wbw_wbr_fifos.v
62	Added BIST signals for RAMs.	mihad	7942d 07h	/pci/tags/rel_3/rtl/verilog/wbw_wbr_fifos.v
59	Added meta flop module for easier meta stable FF identification during synthesis	mihad	7950d 08h	/pci/tags/rel_3/rtl/verilog/wbw_wbr_fifos.v
58	Removed all logic from asynchronous reset network	mihad	7955d 08h	/pci/tags/rel_3/rtl/verilog/wbw_wbr_fifos.v
21	Repaired a few bugs, updated specification, added test bench files and design document	mihad	8191d 09h	/pci/tags/rel_3/rtl/verilog/wbw_wbr_fifos.v
7	Updated all files with inclusion of timescale file for simulation purposes.	mihad	8310d 16h	/pci/tags/rel_3/rtl/verilog/wbw_wbr_fifos.v
2	New project directory structure	mihad	8313d 09h	/pci/tags/rel_3/rtl/verilog/wbw_wbr_fifos.v