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[/] [pci/] [tags/] [rel_3] - Rev 154

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Rev	Log message	Author	Age	Path
154	New directory structure.	root	5584d 07h	/pci/tags/rel_3
74	This commit was manufactured by cvs2svn to create tag 'rel_3'.		7823d 23h	/tags/rel_3
73	Bug fixes, testcases added.	mihad	7823d 23h	/trunk
72	* empty log message *	mihad	7871d 03h	/trunk
71	Changed the code a bit to make it more readable. Functionality not changed in any way. More robust synchronization in fifos is still pending.	mihad	7878d 19h	/trunk
69	Changed BIST signal names etc..	mihad	7916d 02h	/trunk
68	Changed wrong signal name scanb_sen into scanb_en.	tadejm	7919d 12h	/trunk
67	Changed BIST signals for RAMs.	tadejm	7919d 17h	/trunk
66	Changed empty status generation in pciw_fifo_control.v	mihad	7923d 03h	/trunk
65	Cleaned up non-blocking assignments in combinatinal logic statements	mihad	7926d 01h	/trunk
64	The testcase I just added in previous revision repaired	mihad	7926d 03h	/trunk
63	Added additional testcase and changed rst name in BIST to trst	mihad	7926d 05h	/trunk
62	Added BIST signals for RAMs.	mihad	7928d 22h	/trunk
60	Added support for Virtual Silicon two port RAM. Didn't run regression on it yet!	mihad	7936d 22h	/trunk
59	Added meta flop module for easier meta stable FF identification during synthesis	mihad	7936d 23h	/trunk
58	Removed all logic from asynchronous reset network	mihad	7941d 23h	/trunk
57	Added completion expiration test for WB Slave unit. Changed expiration signalling	mihad	7942d 05h	/trunk
56	Number of state bits define was removed	mihad	7942d 20h	/trunk
55	Changed state machine encoding to true one-hot	mihad	7942d 21h	/trunk
54	Changed Tsetup and Thold for WISHBONE models, due to difficulties encountered during gate level sim	mihad	7975d 22h	/trunk

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[/] [pci/] [tags/] [rel_3] - Rev 154

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