URL https://opencores.org/ocsvn/pci/pci/trunk

Subversion Repositories pci

[/] [pci/] [tags/] [rel_5/] [bench/] [verilog/] [system.v] - Rev 64

Rev	Log message	Author	Age	Path
64	The testcase I just added in previous revision repaired	mihad	7942d 01h	/pci/tags/rel_5/bench/verilog/system.v
63	Added additional testcase and changed rst name in BIST to trst	mihad	7942d 03h	/pci/tags/rel_5/bench/verilog/system.v
62	Added BIST signals for RAMs.	mihad	7944d 20h	/pci/tags/rel_5/bench/verilog/system.v
57	Added completion expiration test for WB Slave unit. Changed expiration signalling	mihad	7958d 03h	/pci/tags/rel_5/bench/verilog/system.v
52	Oops, never before noticed that OC header is missing	mihad	7992d 04h	/pci/tags/rel_5/bench/verilog/system.v
51	Fixed a bug and provided testcase for it. Target was responding to configuration cycle type 1 transactions.	mihad	7992d 04h	/pci/tags/rel_5/bench/verilog/system.v
45	Added a few testcases. Repaired wrong reset value for PCI_AM5 register. Repaired Parity Error Detected bit setting. Changed PCI_AM0 to always enabled(regardles of PCI_AM0 define), if image 0 is used as configuration image	mihad	8001d 02h	/pci/tags/rel_5/bench/verilog/system.v
35	Files updated with missing includes, resolved some race conditions in test bench	mihad	8146d 06h	/pci/tags/rel_5/bench/verilog/system.v
33	Added some testcases, removed un-needed fifo signals	mihad	8162d 01h	/pci/tags/rel_5/bench/verilog/system.v
26	Modified testbench and fixed some bugs	mihad	8175d 21h	/pci/tags/rel_5/bench/verilog/system.v
15	Initial testbench import. Still under development	mihad	8194d 00h	/pci/tags/rel_5/bench/verilog/system.v