URL https://opencores.org/ocsvn/pci/pci/trunk

Subversion Repositories pci

[/] [pci/] [tags/] [rel_5/] [bench/] [verilog] - Rev 45

Rev	Log message	Author	Age	Path
45	Added a few testcases. Repaired wrong reset value for PCI_AM5 register. Repaired Parity Error Detected bit setting. Changed PCI_AM0 to always enabled(regardles of PCI_AM0 define), if image 0 is used as configuration image	mihad	8050d 09h	/pci/tags/rel_5/bench/verilog
44	Added for testing of Configuration Cycles Type 1	mihad	8050d 10h	/pci/tags/rel_5/bench/verilog
43	Removed - Interrupt acknowledge cycle now accepted by pci_behaviorial_device	mihad	8050d 10h	/pci/tags/rel_5/bench/verilog
35	Files updated with missing includes, resolved some race conditions in test bench	mihad	8195d 13h	/pci/tags/rel_5/bench/verilog
34	Added missing include statements	mihad	8210d 11h	/pci/tags/rel_5/bench/verilog
33	Added some testcases, removed un-needed fifo signals	mihad	8211d 09h	/pci/tags/rel_5/bench/verilog
26	Modified testbench and fixed some bugs	mihad	8225d 04h	/pci/tags/rel_5/bench/verilog
19	* empty log message *	mihad	8243d 05h	/pci/tags/rel_5/bench/verilog
15	Initial testbench import. Still under development	mihad	8243d 07h	/pci/tags/rel_5/bench/verilog
3	New project directory structure	mihad	8365d 04h	/pci/tags/rel_5/bench/verilog