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[/] [pci/] [tags/] [rel_5/] [bench] - Rev 63

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Rev Log message Author Age Path
63 Added additional testcase and changed rst name in BIST to trst mihad 7933d 04h /pci/tags/rel_5/bench
62 Added BIST signals for RAMs. mihad 7935d 21h /pci/tags/rel_5/bench
57 Added completion expiration test for WB Slave unit. Changed expiration signalling mihad 7949d 04h /pci/tags/rel_5/bench
54 Changed Tsetup and Thold for WISHBONE models, due to difficulties encountered during gate level sim mihad 7982d 21h /pci/tags/rel_5/bench
52 Oops, never before noticed that OC header is missing mihad 7983d 05h /pci/tags/rel_5/bench
51 Fixed a bug and provided testcase for it. Target was responding to configuration cycle type 1 transactions. mihad 7983d 05h /pci/tags/rel_5/bench
45 Added a few testcases. Repaired wrong reset value for PCI_AM5 register. Repaired Parity Error Detected bit setting. Changed PCI_AM0 to always enabled(regardles of PCI_AM0 define), if image 0 is used as configuration image mihad 7992d 03h /pci/tags/rel_5/bench
44 Added for testing of Configuration Cycles Type 1 mihad 7992d 04h /pci/tags/rel_5/bench
43 Removed - Interrupt acknowledge cycle now accepted by pci_behaviorial_device mihad 7992d 04h /pci/tags/rel_5/bench
35 Files updated with missing includes, resolved some race conditions in test bench mihad 8137d 07h /pci/tags/rel_5/bench
34 Added missing include statements mihad 8152d 05h /pci/tags/rel_5/bench
33 Added some testcases, removed un-needed fifo signals mihad 8153d 02h /pci/tags/rel_5/bench
26 Modified testbench and fixed some bugs mihad 8166d 22h /pci/tags/rel_5/bench
19 *** empty log message *** mihad 8184d 23h /pci/tags/rel_5/bench
15 Initial testbench import. Still under development mihad 8185d 00h /pci/tags/rel_5/bench
3 New project directory structure mihad 8306d 22h /pci/tags/rel_5/bench

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