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[/] [pci/] [tags/] [rel_5/] [rtl/] - Rev 154

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Rev	Log message	Author	Age	Path
154	New directory structure.	root	5701d 13h	/pci/tags/rel_5/rtl
82	This commit was manufactured by cvs2svn to create tag 'rel_5'.		7931d 23h	/pci/tags/rel_5/rtl
81	Updated synchronization in top level fifo modules.	mihad	7931d 23h	/pci/tags/rel_5/rtl
79	Updated.	mihad	7935d 04h	/pci/tags/rel_5/rtl
78	Old files with wrong names removed.	mihad	7935d 04h	/pci/tags/rel_5/rtl
77	Changed module and file names. Updated scripts accordingly. FIFO synchronizations changed.	mihad	7935d 04h	/pci/tags/rel_5/rtl
73	Bug fixes, testcases added.	mihad	7941d 05h	/pci/tags/rel_5/rtl
72	* empty log message *	mihad	7988d 09h	/pci/tags/rel_5/rtl
71	Changed the code a bit to make it more readable. Functionality not changed in any way. More robust synchronization in fifos is still pending.	mihad	7996d 00h	/pci/tags/rel_5/rtl
69	Changed BIST signal names etc..	mihad	8033d 08h	/pci/tags/rel_5/rtl
68	Changed wrong signal name scanb_sen into scanb_en.	tadejm	8036d 17h	/pci/tags/rel_5/rtl
67	Changed BIST signals for RAMs.	tadejm	8036d 22h	/pci/tags/rel_5/rtl
66	Changed empty status generation in pciw_fifo_control.v	mihad	8040d 09h	/pci/tags/rel_5/rtl
65	Cleaned up non-blocking assignments in combinatinal logic statements	mihad	8043d 07h	/pci/tags/rel_5/rtl
63	Added additional testcase and changed rst name in BIST to trst	mihad	8043d 11h	/pci/tags/rel_5/rtl
62	Added BIST signals for RAMs.	mihad	8046d 04h	/pci/tags/rel_5/rtl
60	Added support for Virtual Silicon two port RAM. Didn't run regression on it yet!	mihad	8054d 04h	/pci/tags/rel_5/rtl
59	Added meta flop module for easier meta stable FF identification during synthesis	mihad	8054d 05h	/pci/tags/rel_5/rtl
58	Removed all logic from asynchronous reset network	mihad	8059d 05h	/pci/tags/rel_5/rtl
57	Added completion expiration test for WB Slave unit. Changed expiration signalling	mihad	8059d 11h	/pci/tags/rel_5/rtl

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[/] [pci/] [tags/] [rel_5/] [rtl/] - Rev 154

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