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[/] [pci/] [tags/] [rel_5/] [rtl/] - Rev 81

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Rev Log message Author Age Path
81 Updated synchronization in top level fifo modules. mihad 7830d 20h /pci/tags/rel_5/rtl
79 Updated. mihad 7834d 01h /pci/tags/rel_5/rtl
78 Old files with wrong names removed. mihad 7834d 01h /pci/tags/rel_5/rtl
77 Changed module and file names. Updated scripts accordingly. FIFO synchronizations changed. mihad 7834d 01h /pci/tags/rel_5/rtl
73 Bug fixes, testcases added. mihad 7840d 02h /pci/tags/rel_5/rtl
72 *** empty log message *** mihad 7887d 06h /pci/tags/rel_5/rtl
71 Changed the code a bit to make it more readable.
Functionality not changed in any way.
More robust synchronization in fifos is still pending.		 mihad 7894d 21h /pci/tags/rel_5/rtl
69 Changed BIST signal names etc.. mihad 7932d 05h /pci/tags/rel_5/rtl
68 Changed wrong signal name scanb_sen into scanb_en. tadejm 7935d 14h /pci/tags/rel_5/rtl
67 Changed BIST signals for RAMs. tadejm 7935d 19h /pci/tags/rel_5/rtl
66 Changed empty status generation in pciw_fifo_control.v mihad 7939d 06h /pci/tags/rel_5/rtl
65 Cleaned up non-blocking assignments in combinatinal logic statements mihad 7942d 04h /pci/tags/rel_5/rtl
63 Added additional testcase and changed rst name in BIST to trst mihad 7942d 08h /pci/tags/rel_5/rtl
62 Added BIST signals for RAMs. mihad 7945d 01h /pci/tags/rel_5/rtl
60 Added support for Virtual Silicon two port RAM. Didn't run regression on it yet! mihad 7953d 01h /pci/tags/rel_5/rtl
59 Added meta flop module for easier meta stable FF identification during synthesis mihad 7953d 02h /pci/tags/rel_5/rtl
58 Removed all logic from asynchronous reset network mihad 7958d 02h /pci/tags/rel_5/rtl
57 Added completion expiration test for WB Slave unit. Changed expiration signalling mihad 7958d 08h /pci/tags/rel_5/rtl
56 Number of state bits define was removed mihad 7958d 23h /pci/tags/rel_5/rtl
55 Changed state machine encoding to true one-hot mihad 7958d 23h /pci/tags/rel_5/rtl

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