URL https://opencores.org/ocsvn/pci/pci/trunk

Subversion Repositories pci

[/] [pci/] [tags/] [rel_6/] [rtl/] [verilog/] [pci_bridge32.v] - Rev 68

Rev	Log message	Author	Age	Path
68	Changed wrong signal name scanb_sen into scanb_en.	tadejm	7959d 04h	/pci/tags/rel_6/rtl/verilog/pci_bridge32.v
67	Changed BIST signals for RAMs.	tadejm	7959d 09h	/pci/tags/rel_6/rtl/verilog/pci_bridge32.v
63	Added additional testcase and changed rst name in BIST to trst	mihad	7965d 21h	/pci/tags/rel_6/rtl/verilog/pci_bridge32.v
62	Added BIST signals for RAMs.	mihad	7968d 14h	/pci/tags/rel_6/rtl/verilog/pci_bridge32.v
21	Repaired a few bugs, updated specification, added test bench files and design document	mihad	8217d 16h	/pci/tags/rel_6/rtl/verilog/pci_bridge32.v
6	Updated all files with inclusion of timescale file for simulation purposes.	mihad	8336d 23h	/pci/tags/rel_6/rtl/verilog/pci_bridge32.v
2	New project directory structure	mihad	8339d 16h	/pci/tags/rel_6/rtl/verilog/pci_bridge32.v