URL https://opencores.org/ocsvn/pci/pci/trunk

Subversion Repositories pci

[/] [pci/] [tags/] [rel_6/] [rtl/] [verilog/] [pci_target32_interface.v] - Rev 73

Rev	Log message	Author	Age	Path
73	Bug fixes, testcases added.	mihad	7837d 13h	/pci/tags/rel_6/rtl/verilog/pci_target32_interface.v
53	Updated for synthesis purposes. Gate level simulation was failing in some configurations	mihad	7989d 16h	/pci/tags/rel_6/rtl/verilog/pci_target32_interface.v
26	Modified testbench and fixed some bugs	mihad	8173d 13h	/pci/tags/rel_6/rtl/verilog/pci_target32_interface.v
21	Repaired a few bugs, updated specification, added test bench files and design document	mihad	8191d 14h	/pci/tags/rel_6/rtl/verilog/pci_target32_interface.v
6	Updated all files with inclusion of timescale file for simulation purposes.	mihad	8310d 21h	/pci/tags/rel_6/rtl/verilog/pci_target32_interface.v
2	New project directory structure	mihad	8313d 14h	/pci/tags/rel_6/rtl/verilog/pci_target32_interface.v