URL https://opencores.org/ocsvn/pci/pci/trunk

Subversion Repositories pci

[/] [pci/] [tags/] [rel_6/] [rtl/] [verilog/] [pci_target32_sm.v] - Rev 77

Rev	Log message	Author	Age	Path
77	Changed module and file names. Updated scripts accordingly. FIFO synchronizations changed.	mihad	7855d 20h	/pci/tags/rel_6/rtl/verilog/pci_target32_sm.v
73	Bug fixes, testcases added.	mihad	7861d 20h	/pci/tags/rel_6/rtl/verilog/pci_target32_sm.v
56	Number of state bits define was removed	mihad	7980d 17h	/pci/tags/rel_6/rtl/verilog/pci_target32_sm.v
55	Changed state machine encoding to true one-hot	mihad	7980d 18h	/pci/tags/rel_6/rtl/verilog/pci_target32_sm.v
51	Fixed a bug and provided testcase for it. Target was responding to configuration cycle type 1 transactions.	mihad	8014d 03h	/pci/tags/rel_6/rtl/verilog/pci_target32_sm.v
26	Modified testbench and fixed some bugs	mihad	8197d 20h	/pci/tags/rel_6/rtl/verilog/pci_target32_sm.v
21	Repaired a few bugs, updated specification, added test bench files and design document	mihad	8215d 21h	/pci/tags/rel_6/rtl/verilog/pci_target32_sm.v
6	Updated all files with inclusion of timescale file for simulation purposes.	mihad	8335d 04h	/pci/tags/rel_6/rtl/verilog/pci_target32_sm.v
2	New project directory structure	mihad	8337d 21h	/pci/tags/rel_6/rtl/verilog/pci_target32_sm.v