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[/] [pci/] [tags/] [rel_6/] [sim/] - Rev 154

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Rev Log message Author Age Path
154 New directory structure. root 5665d 08h /pci/tags/rel_6/sim
112 This commit was manufactured by cvs2svn to create tag 'rel_6'. 7700d 03h /pci/tags/rel_6/sim
109 There was missing path to hdl.var file. tadejm 7706d 00h /pci/tags/rel_6/sim
106 Added limited WISHBONE B3 support for WISHBONE Slave Unit.
Doesn't support full speed bursts yet.
mihad 7710d 22h /pci/tags/rel_6/sim
104 Found and simulated the problem in the synchronization logic.
Repaired the synchronization logic in the FIFOs.
mihad 7716d 08h /pci/tags/rel_6/sim
95 Removed this file, because it was too large - long download time. mihad 7763d 06h /pci/tags/rel_6/sim
92 Update! mihad 7763d 14h /pci/tags/rel_6/sim
81 Updated synchronization in top level fifo modules. mihad 7895d 18h /pci/tags/rel_6/sim
77 Changed module and file names. Updated scripts accordingly. FIFO synchronizations changed. mihad 7899d 00h /pci/tags/rel_6/sim
73 Bug fixes, testcases added. mihad 7905d 00h /pci/tags/rel_6/sim
72 *** empty log message *** mihad 7952d 04h /pci/tags/rel_6/sim
63 Added additional testcase and changed rst name in BIST to trst mihad 8007d 06h /pci/tags/rel_6/sim
62 Added BIST signals for RAMs. mihad 8009d 23h /pci/tags/rel_6/sim
60 Added support for Virtual Silicon two port RAM. Didn't run regression on it yet! mihad 8017d 23h /pci/tags/rel_6/sim
59 Added meta flop module for easier meta stable FF identification during synthesis mihad 8018d 00h /pci/tags/rel_6/sim
51 Fixed a bug and provided testcase for it. Target was responding to configuration cycle type 1 transactions. mihad 8057d 07h /pci/tags/rel_6/sim
49 Extracted distributed RAM module from wb/pci_tpram.v to its own file, got rid of undef directives mihad 8060d 00h /pci/tags/rel_6/sim
45 Added a few testcases. Repaired wrong reset value for PCI_AM5 register. Repaired Parity Error Detected bit setting. Changed PCI_AM0 to always enabled(regardles of PCI_AM0 define), if image 0 is used as configuration image mihad 8066d 05h /pci/tags/rel_6/sim
42 Removed out of date files mihad 8078d 06h /pci/tags/rel_6/sim
30 Example of PCI testbench log file mihad 8238d 04h /pci/tags/rel_6/sim

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