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[/] [pci/] [tags/] [rel_6/] [sim/] [rtl_sim] - Rev 77

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Rev Log message Author Age Path
77 Changed module and file names. Updated scripts accordingly. FIFO synchronizations changed. mihad 7870d 06h /pci/tags/rel_6/sim/rtl_sim
73 Bug fixes, testcases added. mihad 7876d 06h /pci/tags/rel_6/sim/rtl_sim
72 *** empty log message *** mihad 7923d 10h /pci/tags/rel_6/sim/rtl_sim
63 Added additional testcase and changed rst name in BIST to trst mihad 7978d 12h /pci/tags/rel_6/sim/rtl_sim
62 Added BIST signals for RAMs. mihad 7981d 05h /pci/tags/rel_6/sim/rtl_sim
60 Added support for Virtual Silicon two port RAM. Didn't run regression on it yet! mihad 7989d 05h /pci/tags/rel_6/sim/rtl_sim
59 Added meta flop module for easier meta stable FF identification during synthesis mihad 7989d 06h /pci/tags/rel_6/sim/rtl_sim
51 Fixed a bug and provided testcase for it. Target was responding to configuration cycle type 1 transactions. mihad 8028d 13h /pci/tags/rel_6/sim/rtl_sim
49 Extracted distributed RAM module from wb/pci_tpram.v to its own file, got rid of undef directives mihad 8031d 06h /pci/tags/rel_6/sim/rtl_sim
45 Added a few testcases. Repaired wrong reset value for PCI_AM5 register. Repaired Parity Error Detected bit setting. Changed PCI_AM0 to always enabled(regardles of PCI_AM0 define), if image 0 is used as configuration image mihad 8037d 11h /pci/tags/rel_6/sim/rtl_sim
42 Removed out of date files mihad 8049d 12h /pci/tags/rel_6/sim/rtl_sim
30 Example of PCI testbench log file mihad 8209d 10h /pci/tags/rel_6/sim/rtl_sim
27 Modified testbench and fixed some bugs mihad 8212d 05h /pci/tags/rel_6/sim/rtl_sim
26 Modified testbench and fixed some bugs mihad 8212d 06h /pci/tags/rel_6/sim/rtl_sim
22 Added short description for simulation running mihad 8230d 07h /pci/tags/rel_6/sim/rtl_sim
17 *** empty log message *** mihad 8230d 08h /pci/tags/rel_6/sim/rtl_sim
16 Import of various scripts for simulation running mihad 8230d 09h /pci/tags/rel_6/sim/rtl_sim

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