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[/] [pci/] [tags/] [rel_6] - Rev 94

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Rev Log message Author Age Path
94 Changed one critical PCI bus signal logic. mihad 7735d 01h /pci/tags/rel_6
93 Added a test application! mihad 7735d 08h /pci/tags/rel_6
92 Update! mihad 7735d 08h /pci/tags/rel_6
91 WebPack 5.2 constraint file for PCI CRT application was contributed by Uwe Bonnes (bon@elektron.ikp.physik.tu-darmstadt.de) tadejm 7770d 22h /pci/tags/rel_6
90 WebPack 5.2 project file for PCI CRT application was contributed by Uwe Bonnes (bon@elektron.ikp.physik.tu-darmstadt.de) tadejm 7770d 22h /pci/tags/rel_6
89 Burst 2 error fixed. mihad 7806d 23h /pci/tags/rel_6
88 Added the reset value parameter to the synchronizer flop module.
Added resets to all synchronizer flop instances.
Repaired initial sync value in fifos.		 mihad 7812d 22h /pci/tags/rel_6
87 Updated acording to RTL changes. mihad 7824d 19h /pci/tags/rel_6
86 Entered the option to disable no response counter in wb master. mihad 7824d 19h /pci/tags/rel_6
85 Changed Vendor ID defines. mihad 7825d 00h /pci/tags/rel_6
84 Changed vendor ID. mihad 7828d 18h /pci/tags/rel_6
83 Cleaned up the code. No functional changes. mihad 7853d 17h /pci/tags/rel_6
81 Updated synchronization in top level fifo modules. mihad 7867d 13h /pci/tags/rel_6
79 Updated. mihad 7870d 18h /pci/tags/rel_6
78 Old files with wrong names removed. mihad 7870d 18h /pci/tags/rel_6
77 Changed module and file names. Updated scripts accordingly. FIFO synchronizations changed. mihad 7870d 18h /pci/tags/rel_6
76 TRDY output delay was 10 instead of 11. Repaired. mihad 7873d 18h /pci/tags/rel_6
75 Include statement moved out of off/on pragma as reported by Uwe. mihad 7876d 19h /pci/tags/rel_6
73 Bug fixes, testcases added. mihad 7876d 19h /pci/tags/rel_6
72 *** empty log message *** mihad 7923d 23h /pci/tags/rel_6

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