URL https://opencores.org/ocsvn/pci/pci/trunk

Subversion Repositories pci

[/] [pci/] [tags/] [rel_7/] [bench/] [verilog/] [pci_bus_monitor.v] - Rev 106

Rev	Log message	Author	Age	Path
106	Added limited WISHBONE B3 support for WISHBONE Slave Unit. Doesn't support full speed bursts yet.	mihad	7643d 10h	/pci/tags/rel_7/bench/verilog/pci_bus_monitor.v
45	Added a few testcases. Repaired wrong reset value for PCI_AM5 register. Repaired Parity Error Detected bit setting. Changed PCI_AM0 to always enabled(regardles of PCI_AM0 define), if image 0 is used as configuration image	mihad	7998d 17h	/pci/tags/rel_7/bench/verilog/pci_bus_monitor.v
35	Files updated with missing includes, resolved some race conditions in test bench	mihad	8143d 20h	/pci/tags/rel_7/bench/verilog/pci_bus_monitor.v
15	Initial testbench import. Still under development	mihad	8191d 14h	/pci/tags/rel_7/bench/verilog/pci_bus_monitor.v