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[/] [pci/] [tags/] [rel_7/] [bench/] [verilog/] [pci_testbench_defines.v] - Rev 106

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Rev	Log message	Author	Age	Path
106	Added limited WISHBONE B3 support for WISHBONE Slave Unit. Doesn't support full speed bursts yet.	mihad	7633d 03h	/pci/tags/rel_7/bench/verilog/pci_testbench_defines.v
104	Found and simulated the problem in the synchronization logic. Repaired the synchronization logic in the FIFOs.	mihad	7638d 13h	/pci/tags/rel_7/bench/verilog/pci_testbench_defines.v
92	Update!	mihad	7685d 19h	/pci/tags/rel_7/bench/verilog/pci_testbench_defines.v
73	Bug fixes, testcases added.	mihad	7827d 05h	/pci/tags/rel_7/bench/verilog/pci_testbench_defines.v
69	Changed BIST signal names etc..	mihad	7919d 08h	/pci/tags/rel_7/bench/verilog/pci_testbench_defines.v
66	Changed empty status generation in pciw_fifo_control.v	mihad	7926d 09h	/pci/tags/rel_7/bench/verilog/pci_testbench_defines.v
63	Added additional testcase and changed rst name in BIST to trst	mihad	7929d 11h	/pci/tags/rel_7/bench/verilog/pci_testbench_defines.v
54	Changed Tsetup and Thold for WISHBONE models, due to difficulties encountered during gate level sim	mihad	7979d 04h	/pci/tags/rel_7/bench/verilog/pci_testbench_defines.v
45	Added a few testcases. Repaired wrong reset value for PCI_AM5 register. Repaired Parity Error Detected bit setting. Changed PCI_AM0 to always enabled(regardles of PCI_AM0 define), if image 0 is used as configuration image	mihad	7988d 10h	/pci/tags/rel_7/bench/verilog/pci_testbench_defines.v
26	Modified testbench and fixed some bugs	mihad	8163d 05h	/pci/tags/rel_7/bench/verilog/pci_testbench_defines.v
15	Initial testbench import. Still under development	mihad	8181d 08h	/pci/tags/rel_7/bench/verilog/pci_testbench_defines.v

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