URL https://opencores.org/ocsvn/pci/pci/trunk

Subversion Repositories pci

[/] [pci/] [tags/] [rel_7/] [bench/] [verilog/] [pci_testbench_defines.v] - Rev 54

Rev	Log message	Author	Age	Path
54	Changed Tsetup and Thold for WISHBONE models, due to difficulties encountered during gate level sim	mihad	7979d 04h	/pci/tags/rel_7/bench/verilog/pci_testbench_defines.v
45	Added a few testcases. Repaired wrong reset value for PCI_AM5 register. Repaired Parity Error Detected bit setting. Changed PCI_AM0 to always enabled(regardles of PCI_AM0 define), if image 0 is used as configuration image	mihad	7988d 10h	/pci/tags/rel_7/bench/verilog/pci_testbench_defines.v
26	Modified testbench and fixed some bugs	mihad	8163d 05h	/pci/tags/rel_7/bench/verilog/pci_testbench_defines.v
15	Initial testbench import. Still under development	mihad	8181d 08h	/pci/tags/rel_7/bench/verilog/pci_testbench_defines.v