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[/] [pci/] [tags/] [rel_7/] [bench/] [verilog/] [system.v] - Rev 73

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Rev Log message Author Age Path
73 Bug fixes, testcases added. mihad 7828d 04h /pci/tags/rel_7/bench/verilog/system.v
69 Changed BIST signal names etc.. mihad 7920d 07h /pci/tags/rel_7/bench/verilog/system.v
64 The testcase I just added in previous revision repaired mihad 7930d 08h /pci/tags/rel_7/bench/verilog/system.v
63 Added additional testcase and changed rst name in BIST to trst mihad 7930d 10h /pci/tags/rel_7/bench/verilog/system.v
62 Added BIST signals for RAMs. mihad 7933d 02h /pci/tags/rel_7/bench/verilog/system.v
57 Added completion expiration test for WB Slave unit. Changed expiration signalling mihad 7946d 10h /pci/tags/rel_7/bench/verilog/system.v
52 Oops, never before noticed that OC header is missing mihad 7980d 10h /pci/tags/rel_7/bench/verilog/system.v
51 Fixed a bug and provided testcase for it. Target was responding to configuration cycle type 1 transactions. mihad 7980d 11h /pci/tags/rel_7/bench/verilog/system.v
45 Added a few testcases. Repaired wrong reset value for PCI_AM5 register. Repaired Parity Error Detected bit setting. Changed PCI_AM0 to always enabled(regardles of PCI_AM0 define), if image 0 is used as configuration image mihad 7989d 09h /pci/tags/rel_7/bench/verilog/system.v
35 Files updated with missing includes, resolved some race conditions in test bench mihad 8134d 12h /pci/tags/rel_7/bench/verilog/system.v
33 Added some testcases, removed un-needed fifo signals mihad 8150d 08h /pci/tags/rel_7/bench/verilog/system.v
26 Modified testbench and fixed some bugs mihad 8164d 03h /pci/tags/rel_7/bench/verilog/system.v
15 Initial testbench import. Still under development mihad 8182d 06h /pci/tags/rel_7/bench/verilog/system.v

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