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[/] [pci/] [tags/] [rel_7/] [bench/] [verilog] - Rev 154

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Rev	Log message	Author	Age	Path
154	New directory structure.	root	5638d 11h	/pci/tags/rel_7/bench/verilog
114	This commit was manufactured by cvs2svn to create tag 'rel_7'.		7673d 01h	/pci/tags/rel_7/bench/verilog
107	Added status when checking disconnect with or without data. Before it was only retry, now there is stop and retry.	tadejm	7679d 03h	/pci/tags/rel_7/bench/verilog
106	Added limited WISHBONE B3 support for WISHBONE Slave Unit. Doesn't support full speed bursts yet.	mihad	7684d 01h	/pci/tags/rel_7/bench/verilog
104	Found and simulated the problem in the synchronization logic. Repaired the synchronization logic in the FIFOs.	mihad	7689d 11h	/pci/tags/rel_7/bench/verilog
92	Update!	mihad	7736d 17h	/pci/tags/rel_7/bench/verilog
89	Burst 2 error fixed.	mihad	7808d 07h	/pci/tags/rel_7/bench/verilog
87	Updated acording to RTL changes.	mihad	7826d 04h	/pci/tags/rel_7/bench/verilog
81	Updated synchronization in top level fifo modules.	mihad	7868d 21h	/pci/tags/rel_7/bench/verilog
73	Bug fixes, testcases added.	mihad	7878d 03h	/pci/tags/rel_7/bench/verilog
69	Changed BIST signal names etc..	mihad	7970d 06h	/pci/tags/rel_7/bench/verilog
66	Changed empty status generation in pciw_fifo_control.v	mihad	7977d 07h	/pci/tags/rel_7/bench/verilog
64	The testcase I just added in previous revision repaired	mihad	7980d 07h	/pci/tags/rel_7/bench/verilog
63	Added additional testcase and changed rst name in BIST to trst	mihad	7980d 09h	/pci/tags/rel_7/bench/verilog
62	Added BIST signals for RAMs.	mihad	7983d 02h	/pci/tags/rel_7/bench/verilog
57	Added completion expiration test for WB Slave unit. Changed expiration signalling	mihad	7996d 09h	/pci/tags/rel_7/bench/verilog
54	Changed Tsetup and Thold for WISHBONE models, due to difficulties encountered during gate level sim	mihad	8030d 02h	/pci/tags/rel_7/bench/verilog
52	Oops, never before noticed that OC header is missing	mihad	8030d 10h	/pci/tags/rel_7/bench/verilog
51	Fixed a bug and provided testcase for it. Target was responding to configuration cycle type 1 transactions.	mihad	8030d 10h	/pci/tags/rel_7/bench/verilog
45	Added a few testcases. Repaired wrong reset value for PCI_AM5 register. Repaired Parity Error Detected bit setting. Changed PCI_AM0 to always enabled(regardles of PCI_AM0 define), if image 0 is used as configuration image	mihad	8039d 08h	/pci/tags/rel_7/bench/verilog

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[/] [pci/] [tags/] [rel_7/] [bench/] [verilog] - Rev 154

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