URL https://opencores.org/ocsvn/pci/pci/trunk

Subversion Repositories pci

[/] [pci/] [tags/] [rel_7/] [rtl/] [verilog/] [pci_bridge32.v] - Rev 106

Rev	Log message	Author	Age	Path
106	Added limited WISHBONE B3 support for WISHBONE Slave Unit. Doesn't support full speed bursts yet.	mihad	7648d 11h	/pci/tags/rel_7/rtl/verilog/pci_bridge32.v
77	Changed module and file names. Updated scripts accordingly. FIFO synchronizations changed.	mihad	7836d 13h	/pci/tags/rel_7/rtl/verilog/pci_bridge32.v
69	Changed BIST signal names etc..	mihad	7934d 16h	/pci/tags/rel_7/rtl/verilog/pci_bridge32.v
68	Changed wrong signal name scanb_sen into scanb_en.	tadejm	7938d 02h	/pci/tags/rel_7/rtl/verilog/pci_bridge32.v
67	Changed BIST signals for RAMs.	tadejm	7938d 07h	/pci/tags/rel_7/rtl/verilog/pci_bridge32.v
63	Added additional testcase and changed rst name in BIST to trst	mihad	7944d 19h	/pci/tags/rel_7/rtl/verilog/pci_bridge32.v
62	Added BIST signals for RAMs.	mihad	7947d 12h	/pci/tags/rel_7/rtl/verilog/pci_bridge32.v
21	Repaired a few bugs, updated specification, added test bench files and design document	mihad	8196d 14h	/pci/tags/rel_7/rtl/verilog/pci_bridge32.v
6	Updated all files with inclusion of timescale file for simulation purposes.	mihad	8315d 21h	/pci/tags/rel_7/rtl/verilog/pci_bridge32.v
2	New project directory structure	mihad	8318d 14h	/pci/tags/rel_7/rtl/verilog/pci_bridge32.v