URL https://opencores.org/ocsvn/pci/pci/trunk

Subversion Repositories pci

[/] [pci/] [tags/] [rel_7/] [rtl/] [verilog/] [pci_parity_check.v] - Rev 45

Rev	Log message	Author	Age	Path
45	Added a few testcases. Repaired wrong reset value for PCI_AM5 register. Repaired Parity Error Detected bit setting. Changed PCI_AM0 to always enabled(regardles of PCI_AM0 define), if image 0 is used as configuration image	mihad	7996d 09h	/pci/tags/rel_7/rtl/verilog/pci_parity_check.v
21	Repaired a few bugs, updated specification, added test bench files and design document	mihad	8189d 04h	/pci/tags/rel_7/rtl/verilog/pci_parity_check.v
6	Updated all files with inclusion of timescale file for simulation purposes.	mihad	8308d 12h	/pci/tags/rel_7/rtl/verilog/pci_parity_check.v
2	New project directory structure	mihad	8311d 04h	/pci/tags/rel_7/rtl/verilog/pci_parity_check.v