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[/] [pci/] [tags/] [rel_7/] [rtl/] [verilog/] [pci_target_unit.v] - Rev 154

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Rev Log message Author Age Path
154 New directory structure. root 5630d 07h /pci/tags/rel_7/rtl/verilog/pci_target_unit.v
114 This commit was manufactured by cvs2svn to create tag 'rel_7'. 7664d 21h /pci/tags/rel_7/rtl/verilog/pci_target_unit.v
108 Added 'three_left_out' to pci_pciw_fifo signaling three locations before full. Added comparison between current registered cbe and next unregistered cbe to signal wb_master whether it is allowed to performe burst or not. Due to this, I needed 'three_left_out' so that writing to pci_pciw_fifo can be registered, otherwise timing problems would occure. tadejm 7670d 23h /pci/tags/rel_7/rtl/verilog/pci_target_unit.v
77 Changed module and file names. Updated scripts accordingly. FIFO synchronizations changed. mihad 7863d 22h /pci/tags/rel_7/rtl/verilog/pci_target_unit.v
68 Changed wrong signal name scanb_sen into scanb_en. tadejm 7965d 12h /pci/tags/rel_7/rtl/verilog/pci_target_unit.v
67 Changed BIST signals for RAMs. tadejm 7965d 16h /pci/tags/rel_7/rtl/verilog/pci_target_unit.v
63 Added additional testcase and changed rst name in BIST to trst mihad 7972d 05h /pci/tags/rel_7/rtl/verilog/pci_target_unit.v
62 Added BIST signals for RAMs. mihad 7974d 22h /pci/tags/rel_7/rtl/verilog/pci_target_unit.v
58 Removed all logic from asynchronous reset network mihad 7987d 23h /pci/tags/rel_7/rtl/verilog/pci_target_unit.v
33 Added some testcases, removed un-needed fifo signals mihad 8192d 03h /pci/tags/rel_7/rtl/verilog/pci_target_unit.v
26 Modified testbench and fixed some bugs mihad 8205d 23h /pci/tags/rel_7/rtl/verilog/pci_target_unit.v
21 Repaired a few bugs, updated specification, added test bench files and design document mihad 8224d 00h /pci/tags/rel_7/rtl/verilog/pci_target_unit.v
6 Updated all files with inclusion of timescale file for simulation purposes. mihad 8343d 07h /pci/tags/rel_7/rtl/verilog/pci_target_unit.v
2 New project directory structure mihad 8346d 00h /pci/tags/rel_7/rtl/verilog/pci_target_unit.v

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