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[/] [pci/] [tags/] [rel_7/] [rtl] - Rev 63

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Rev Log message Author Age Path
63 Added additional testcase and changed rst name in BIST to trst mihad 8010d 06h /pci/tags/rel_7/rtl
62 Added BIST signals for RAMs. mihad 8012d 23h /pci/tags/rel_7/rtl
60 Added support for Virtual Silicon two port RAM. Didn't run regression on it yet! mihad 8020d 23h /pci/tags/rel_7/rtl
59 Added meta flop module for easier meta stable FF identification during synthesis mihad 8021d 00h /pci/tags/rel_7/rtl
58 Removed all logic from asynchronous reset network mihad 8026d 00h /pci/tags/rel_7/rtl
57 Added completion expiration test for WB Slave unit. Changed expiration signalling mihad 8026d 06h /pci/tags/rel_7/rtl
56 Number of state bits define was removed mihad 8026d 21h /pci/tags/rel_7/rtl
55 Changed state machine encoding to true one-hot mihad 8026d 22h /pci/tags/rel_7/rtl
53 Updated for synthesis purposes. Gate level simulation was failing in some configurations mihad 8060d 03h /pci/tags/rel_7/rtl
51 Fixed a bug and provided testcase for it. Target was responding to configuration cycle type 1 transactions. mihad 8060d 07h /pci/tags/rel_7/rtl
50 Got rid of undef directives mihad 8062d 23h /pci/tags/rel_7/rtl
49 Extracted distributed RAM module from wb/pci_tpram.v to its own file, got rid of undef directives mihad 8062d 23h /pci/tags/rel_7/rtl
48 Extracted distributed RAM module from wb/pci_tpram.v to its own file mihad 8062d 23h /pci/tags/rel_7/rtl
47 Known issues repaired mihad 8063d 05h /pci/tags/rel_7/rtl
46 Include statement was enclosed in synosys translate off/on directive - repaired mihad 8068d 00h /pci/tags/rel_7/rtl
45 Added a few testcases. Repaired wrong reset value for PCI_AM5 register. Repaired Parity Error Detected bit setting. Changed PCI_AM0 to always enabled(regardles of PCI_AM0 define), if image 0 is used as configuration image mihad 8069d 05h /pci/tags/rel_7/rtl
35 Files updated with missing includes, resolved some race conditions in test bench mihad 8214d 09h /pci/tags/rel_7/rtl
33 Added some testcases, removed un-needed fifo signals mihad 8230d 04h /pci/tags/rel_7/rtl
32 Added include statement that was missing and causing errors mihad 8238d 01h /pci/tags/rel_7/rtl
26 Modified testbench and fixed some bugs mihad 8244d 00h /pci/tags/rel_7/rtl

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