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[/] [pci/] [tags/] [rel_7/] [rtl] - Rev 88

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Rev Log message Author Age Path
88 Added the reset value parameter to the synchronizer flop module.
Added resets to all synchronizer flop instances.
Repaired initial sync value in fifos.
mihad 7773d 14h /pci/tags/rel_7/rtl
86 Entered the option to disable no response counter in wb master. mihad 7785d 12h /pci/tags/rel_7/rtl
83 Cleaned up the code. No functional changes. mihad 7814d 09h /pci/tags/rel_7/rtl
81 Updated synchronization in top level fifo modules. mihad 7828d 05h /pci/tags/rel_7/rtl
79 Updated. mihad 7831d 10h /pci/tags/rel_7/rtl
78 Old files with wrong names removed. mihad 7831d 10h /pci/tags/rel_7/rtl
77 Changed module and file names. Updated scripts accordingly. FIFO synchronizations changed. mihad 7831d 10h /pci/tags/rel_7/rtl
73 Bug fixes, testcases added. mihad 7837d 11h /pci/tags/rel_7/rtl
72 *** empty log message *** mihad 7884d 15h /pci/tags/rel_7/rtl
71 Changed the code a bit to make it more readable.
Functionality not changed in any way.
More robust synchronization in fifos is still pending.
mihad 7892d 07h /pci/tags/rel_7/rtl
69 Changed BIST signal names etc.. mihad 7929d 14h /pci/tags/rel_7/rtl
68 Changed wrong signal name scanb_sen into scanb_en. tadejm 7933d 00h /pci/tags/rel_7/rtl
67 Changed BIST signals for RAMs. tadejm 7933d 04h /pci/tags/rel_7/rtl
66 Changed empty status generation in pciw_fifo_control.v mihad 7936d 15h /pci/tags/rel_7/rtl
65 Cleaned up non-blocking assignments in combinatinal logic statements mihad 7939d 13h /pci/tags/rel_7/rtl
63 Added additional testcase and changed rst name in BIST to trst mihad 7939d 17h /pci/tags/rel_7/rtl
62 Added BIST signals for RAMs. mihad 7942d 10h /pci/tags/rel_7/rtl
60 Added support for Virtual Silicon two port RAM. Didn't run regression on it yet! mihad 7950d 10h /pci/tags/rel_7/rtl
59 Added meta flop module for easier meta stable FF identification during synthesis mihad 7950d 11h /pci/tags/rel_7/rtl
58 Removed all logic from asynchronous reset network mihad 7955d 11h /pci/tags/rel_7/rtl

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