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[/] [pci/] [tags/] [rel_7/] [rtl] - Rev 88

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Rev Log message Author Age Path
88 Added the reset value parameter to the synchronizer flop module.
Added resets to all synchronizer flop instances.
Repaired initial sync value in fifos.
mihad 7796d 11h /pci/tags/rel_7/rtl
86 Entered the option to disable no response counter in wb master. mihad 7808d 09h /pci/tags/rel_7/rtl
83 Cleaned up the code. No functional changes. mihad 7837d 06h /pci/tags/rel_7/rtl
81 Updated synchronization in top level fifo modules. mihad 7851d 02h /pci/tags/rel_7/rtl
79 Updated. mihad 7854d 07h /pci/tags/rel_7/rtl
78 Old files with wrong names removed. mihad 7854d 07h /pci/tags/rel_7/rtl
77 Changed module and file names. Updated scripts accordingly. FIFO synchronizations changed. mihad 7854d 07h /pci/tags/rel_7/rtl
73 Bug fixes, testcases added. mihad 7860d 08h /pci/tags/rel_7/rtl
72 *** empty log message *** mihad 7907d 12h /pci/tags/rel_7/rtl
71 Changed the code a bit to make it more readable.
Functionality not changed in any way.
More robust synchronization in fifos is still pending.
mihad 7915d 03h /pci/tags/rel_7/rtl
69 Changed BIST signal names etc.. mihad 7952d 11h /pci/tags/rel_7/rtl
68 Changed wrong signal name scanb_sen into scanb_en. tadejm 7955d 20h /pci/tags/rel_7/rtl
67 Changed BIST signals for RAMs. tadejm 7956d 01h /pci/tags/rel_7/rtl
66 Changed empty status generation in pciw_fifo_control.v mihad 7959d 12h /pci/tags/rel_7/rtl
65 Cleaned up non-blocking assignments in combinatinal logic statements mihad 7962d 10h /pci/tags/rel_7/rtl
63 Added additional testcase and changed rst name in BIST to trst mihad 7962d 14h /pci/tags/rel_7/rtl
62 Added BIST signals for RAMs. mihad 7965d 07h /pci/tags/rel_7/rtl
60 Added support for Virtual Silicon two port RAM. Didn't run regression on it yet! mihad 7973d 07h /pci/tags/rel_7/rtl
59 Added meta flop module for easier meta stable FF identification during synthesis mihad 7973d 08h /pci/tags/rel_7/rtl
58 Removed all logic from asynchronous reset network mihad 7978d 08h /pci/tags/rel_7/rtl

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