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[/] [pci/] [tags/] [rel_8/] [rtl/] - Rev 154

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Rev Log message Author Age Path
154 New directory structure. root 5583d 11h /pci/tags/rel_8/rtl
120 This commit was manufactured by cvs2svn to create tag 'rel_8'. 7610d 23h /pci/tags/rel_8/rtl
117 WB Master is now WISHBONE B3 compatible. tadejm 7610d 23h /pci/tags/rel_8/rtl
116 Corrected bug when writing to FIFO (now it is registered). tadejm 7610d 23h /pci/tags/rel_8/rtl
115 Added signals for WB Master B3. tadejm 7610d 23h /pci/tags/rel_8/rtl
113 ifdefs moved to thier own lines, this confuses some of the tools. simons 7618d 02h /pci/tags/rel_8/rtl
111 synchronizer_flop replaced with pci_synchronizer_flop, artisan ram instance updated. simons 7618d 07h /pci/tags/rel_8/rtl
110 Module that converts slave WISHBONE B3 accesses to
WISHBONE B2 accesses with CAB.
mihad 7620d 06h /pci/tags/rel_8/rtl
108 Added 'three_left_out' to pci_pciw_fifo signaling three locations before full. Added comparison between current registered cbe and next unregistered cbe to signal wb_master whether it is allowed to performe burst or not. Due to this, I needed 'three_left_out' so that writing to pci_pciw_fifo can be registered, otherwise timing problems would occure. tadejm 7624d 03h /pci/tags/rel_8/rtl
106 Added limited WISHBONE B3 support for WISHBONE Slave Unit.
Doesn't support full speed bursts yet.
mihad 7629d 02h /pci/tags/rel_8/rtl
104 Found and simulated the problem in the synchronization logic.
Repaired the synchronization logic in the FIFOs.
mihad 7634d 11h /pci/tags/rel_8/rtl
94 Changed one critical PCI bus signal logic. mihad 7681d 09h /pci/tags/rel_8/rtl
88 Added the reset value parameter to the synchronizer flop module.
Added resets to all synchronizer flop instances.
Repaired initial sync value in fifos.
mihad 7759d 06h /pci/tags/rel_8/rtl
86 Entered the option to disable no response counter in wb master. mihad 7771d 04h /pci/tags/rel_8/rtl
83 Cleaned up the code. No functional changes. mihad 7800d 01h /pci/tags/rel_8/rtl
81 Updated synchronization in top level fifo modules. mihad 7813d 22h /pci/tags/rel_8/rtl
79 Updated. mihad 7817d 03h /pci/tags/rel_8/rtl
78 Old files with wrong names removed. mihad 7817d 03h /pci/tags/rel_8/rtl
77 Changed module and file names. Updated scripts accordingly. FIFO synchronizations changed. mihad 7817d 03h /pci/tags/rel_8/rtl
73 Bug fixes, testcases added. mihad 7823d 04h /pci/tags/rel_8/rtl

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