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[/] [pci/] [tags/] [rel_8/] [rtl/] - Rev 81

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Rev Log message Author Age Path
81 Updated synchronization in top level fifo modules. mihad 7813d 23h /pci/tags/rel_8/rtl
79 Updated. mihad 7817d 04h /pci/tags/rel_8/rtl
78 Old files with wrong names removed. mihad 7817d 04h /pci/tags/rel_8/rtl
77 Changed module and file names. Updated scripts accordingly. FIFO synchronizations changed. mihad 7817d 04h /pci/tags/rel_8/rtl
73 Bug fixes, testcases added. mihad 7823d 05h /pci/tags/rel_8/rtl
72 *** empty log message *** mihad 7870d 09h /pci/tags/rel_8/rtl
71 Changed the code a bit to make it more readable.
Functionality not changed in any way.
More robust synchronization in fifos is still pending.		 mihad 7878d 01h /pci/tags/rel_8/rtl
69 Changed BIST signal names etc.. mihad 7915d 08h /pci/tags/rel_8/rtl
68 Changed wrong signal name scanb_sen into scanb_en. tadejm 7918d 18h /pci/tags/rel_8/rtl
67 Changed BIST signals for RAMs. tadejm 7918d 22h /pci/tags/rel_8/rtl
66 Changed empty status generation in pciw_fifo_control.v mihad 7922d 09h /pci/tags/rel_8/rtl
65 Cleaned up non-blocking assignments in combinatinal logic statements mihad 7925d 07h /pci/tags/rel_8/rtl
63 Added additional testcase and changed rst name in BIST to trst mihad 7925d 11h /pci/tags/rel_8/rtl
62 Added BIST signals for RAMs. mihad 7928d 04h /pci/tags/rel_8/rtl
60 Added support for Virtual Silicon two port RAM. Didn't run regression on it yet! mihad 7936d 04h /pci/tags/rel_8/rtl
59 Added meta flop module for easier meta stable FF identification during synthesis mihad 7936d 05h /pci/tags/rel_8/rtl
58 Removed all logic from asynchronous reset network mihad 7941d 05h /pci/tags/rel_8/rtl
57 Added completion expiration test for WB Slave unit. Changed expiration signalling mihad 7941d 11h /pci/tags/rel_8/rtl
56 Number of state bits define was removed mihad 7942d 02h /pci/tags/rel_8/rtl
55 Changed state machine encoding to true one-hot mihad 7942d 03h /pci/tags/rel_8/rtl

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