URL https://opencores.org/ocsvn/pci/pci/trunk

Subversion Repositories pci

[/] [pci/] [tags/] [rel_8/] [rtl/] [verilog/] [top.v] - Rev 154

Rev	Log message	Author	Age	Path
154	New directory structure.	root	5608d 11h	/pci/tags/rel_8/rtl/verilog/top.v
120	This commit was manufactured by cvs2svn to create tag 'rel_8'.		7635d 22h	/pci/tags/rel_8/rtl/verilog/top.v
115	Added signals for WB Master B3.	tadejm	7635d 22h	/pci/tags/rel_8/rtl/verilog/top.v
106	Added limited WISHBONE B3 support for WISHBONE Slave Unit. Doesn't support full speed bursts yet.	mihad	7654d 01h	/pci/tags/rel_8/rtl/verilog/top.v
77	Changed module and file names. Updated scripts accordingly. FIFO synchronizations changed.	mihad	7842d 02h	/pci/tags/rel_8/rtl/verilog/top.v
68	Changed wrong signal name scanb_sen into scanb_en.	tadejm	7943d 15h	/pci/tags/rel_8/rtl/verilog/top.v
67	Changed BIST signals for RAMs.	tadejm	7943d 20h	/pci/tags/rel_8/rtl/verilog/top.v
63	Added additional testcase and changed rst name in BIST to trst	mihad	7950d 09h	/pci/tags/rel_8/rtl/verilog/top.v
62	Added BIST signals for RAMs.	mihad	7953d 02h	/pci/tags/rel_8/rtl/verilog/top.v
35	Files updated with missing includes, resolved some race conditions in test bench	mihad	8154d 11h	/pci/tags/rel_8/rtl/verilog/top.v
21	Repaired a few bugs, updated specification, added test bench files and design document	mihad	8202d 04h	/pci/tags/rel_8/rtl/verilog/top.v
6	Updated all files with inclusion of timescale file for simulation purposes.	mihad	8321d 11h	/pci/tags/rel_8/rtl/verilog/top.v
2	New project directory structure	mihad	8324d 03h	/pci/tags/rel_8/rtl/verilog/top.v