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[/] [pci/] [tags/] [rel_8] - Rev 90

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Rev Log message Author Age Path
90 WebPack 5.2 project file for PCI CRT application was contributed by Uwe Bonnes (bon@elektron.ikp.physik.tu-darmstadt.de) tadejm 7804d 12h /pci/tags/rel_8
89 Burst 2 error fixed. mihad 7840d 13h /pci/tags/rel_8
88 Added the reset value parameter to the synchronizer flop module.
Added resets to all synchronizer flop instances.
Repaired initial sync value in fifos.		 mihad 7846d 12h /pci/tags/rel_8
87 Updated acording to RTL changes. mihad 7858d 10h /pci/tags/rel_8
86 Entered the option to disable no response counter in wb master. mihad 7858d 10h /pci/tags/rel_8
85 Changed Vendor ID defines. mihad 7858d 14h /pci/tags/rel_8
84 Changed vendor ID. mihad 7862d 08h /pci/tags/rel_8
83 Cleaned up the code. No functional changes. mihad 7887d 07h /pci/tags/rel_8
81 Updated synchronization in top level fifo modules. mihad 7901d 03h /pci/tags/rel_8
79 Updated. mihad 7904d 08h /pci/tags/rel_8
78 Old files with wrong names removed. mihad 7904d 08h /pci/tags/rel_8
77 Changed module and file names. Updated scripts accordingly. FIFO synchronizations changed. mihad 7904d 08h /pci/tags/rel_8
76 TRDY output delay was 10 instead of 11. Repaired. mihad 7907d 08h /pci/tags/rel_8
75 Include statement moved out of off/on pragma as reported by Uwe. mihad 7910d 09h /pci/tags/rel_8
73 Bug fixes, testcases added. mihad 7910d 09h /pci/tags/rel_8
72 *** empty log message *** mihad 7957d 13h /pci/tags/rel_8
71 Changed the code a bit to make it more readable.
Functionality not changed in any way.
More robust synchronization in fifos is still pending.		 mihad 7965d 05h /pci/tags/rel_8
69 Changed BIST signal names etc.. mihad 8002d 12h /pci/tags/rel_8
68 Changed wrong signal name scanb_sen into scanb_en. tadejm 8005d 22h /pci/tags/rel_8
67 Changed BIST signals for RAMs. tadejm 8006d 02h /pci/tags/rel_8

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