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[/] [pci/] [tags/] [rel_9] - Rev 95

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Rev Log message Author Age Path
95 Removed this file, because it was too large - long download time. mihad 7705d 13h /pci/tags/rel_9
94 Changed one critical PCI bus signal logic. mihad 7705d 13h /pci/tags/rel_9
93 Added a test application! mihad 7705d 21h /pci/tags/rel_9
92 Update! mihad 7705d 21h /pci/tags/rel_9
91 WebPack 5.2 constraint file for PCI CRT application was contributed by Uwe Bonnes (bon@elektron.ikp.physik.tu-darmstadt.de) tadejm 7741d 11h /pci/tags/rel_9
90 WebPack 5.2 project file for PCI CRT application was contributed by Uwe Bonnes (bon@elektron.ikp.physik.tu-darmstadt.de) tadejm 7741d 11h /pci/tags/rel_9
89 Burst 2 error fixed. mihad 7777d 11h /pci/tags/rel_9
88 Added the reset value parameter to the synchronizer flop module.
Added resets to all synchronizer flop instances.
Repaired initial sync value in fifos.		 mihad 7783d 10h /pci/tags/rel_9
87 Updated acording to RTL changes. mihad 7795d 08h /pci/tags/rel_9
86 Entered the option to disable no response counter in wb master. mihad 7795d 08h /pci/tags/rel_9
85 Changed Vendor ID defines. mihad 7795d 12h /pci/tags/rel_9
84 Changed vendor ID. mihad 7799d 07h /pci/tags/rel_9
83 Cleaned up the code. No functional changes. mihad 7824d 05h /pci/tags/rel_9
81 Updated synchronization in top level fifo modules. mihad 7838d 02h /pci/tags/rel_9
79 Updated. mihad 7841d 07h /pci/tags/rel_9
78 Old files with wrong names removed. mihad 7841d 07h /pci/tags/rel_9
77 Changed module and file names. Updated scripts accordingly. FIFO synchronizations changed. mihad 7841d 07h /pci/tags/rel_9
76 TRDY output delay was 10 instead of 11. Repaired. mihad 7844d 06h /pci/tags/rel_9
75 Include statement moved out of off/on pragma as reported by Uwe. mihad 7847d 07h /pci/tags/rel_9
73 Bug fixes, testcases added. mihad 7847d 08h /pci/tags/rel_9

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