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[/] [pci/] [tags/] [rel_WB_B3/] [apps] - Rev 96

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Rev Log message Author Age Path
96 Update! mihad 7706d 08h /pci/tags/rel_WB_B3/apps
93 Added a test application! mihad 7706d 15h /pci/tags/rel_WB_B3/apps
91 WebPack 5.2 constraint file for PCI CRT application was contributed by Uwe Bonnes (bon@elektron.ikp.physik.tu-darmstadt.de) tadejm 7742d 05h /pci/tags/rel_WB_B3/apps
90 WebPack 5.2 project file for PCI CRT application was contributed by Uwe Bonnes (bon@elektron.ikp.physik.tu-darmstadt.de) tadejm 7742d 05h /pci/tags/rel_WB_B3/apps
85 Changed Vendor ID defines. mihad 7796d 06h /pci/tags/rel_WB_B3/apps
84 Changed vendor ID. mihad 7800d 01h /pci/tags/rel_WB_B3/apps
77 Changed module and file names. Updated scripts accordingly. FIFO synchronizations changed. mihad 7842d 01h /pci/tags/rel_WB_B3/apps
76 TRDY output delay was 10 instead of 11. Repaired. mihad 7845d 01h /pci/tags/rel_WB_B3/apps
75 Include statement moved out of off/on pragma as reported by Uwe. mihad 7848d 01h /pci/tags/rel_WB_B3/apps
59 Added meta flop module for easier meta stable FF identification during synthesis mihad 7961d 02h /pci/tags/rel_WB_B3/apps
38 This file is not needed tadej 8100d 02h /pci/tags/rel_WB_B3/apps
36 *** empty log message *** tadej 8100d 03h /pci/tags/rel_WB_B3/apps
31 User defined constants used for Test Application tadej 8180d 22h /pci/tags/rel_WB_B3/apps
29 Xilinx synthesys log file tadej 8181d 08h /pci/tags/rel_WB_B3/apps
25 *** empty log message *** mihad 8202d 00h /pci/tags/rel_WB_B3/apps
21 Repaired a few bugs, updated specification, added test bench files and design document mihad 8202d 02h /pci/tags/rel_WB_B3/apps
14 *** empty log message *** mihad 8202d 04h /pci/tags/rel_WB_B3/apps
5 Added .o file for kernel 2.4.3 mihad 8324d 01h /pci/tags/rel_WB_B3/apps
3 New project directory structure mihad 8324d 02h /pci/tags/rel_WB_B3/apps
2 New project directory structure mihad 8324d 02h /pci/tags/rel_WB_B3/apps

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