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[/] [pci/] [tags/] [rel_WB_B3/] [bench] - Rev 62

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Rev Log message Author Age Path
62 Added BIST signals for RAMs. mihad 7981d 15h /pci/tags/rel_WB_B3/bench
57 Added completion expiration test for WB Slave unit. Changed expiration signalling mihad 7994d 22h /pci/tags/rel_WB_B3/bench
54 Changed Tsetup and Thold for WISHBONE models, due to difficulties encountered during gate level sim mihad 8028d 15h /pci/tags/rel_WB_B3/bench
52 Oops, never before noticed that OC header is missing mihad 8028d 23h /pci/tags/rel_WB_B3/bench
51 Fixed a bug and provided testcase for it. Target was responding to configuration cycle type 1 transactions. mihad 8028d 23h /pci/tags/rel_WB_B3/bench
45 Added a few testcases. Repaired wrong reset value for PCI_AM5 register. Repaired Parity Error Detected bit setting. Changed PCI_AM0 to always enabled(regardles of PCI_AM0 define), if image 0 is used as configuration image mihad 8037d 21h /pci/tags/rel_WB_B3/bench
44 Added for testing of Configuration Cycles Type 1 mihad 8037d 22h /pci/tags/rel_WB_B3/bench
43 Removed - Interrupt acknowledge cycle now accepted by pci_behaviorial_device mihad 8037d 22h /pci/tags/rel_WB_B3/bench
35 Files updated with missing includes, resolved some race conditions in test bench mihad 8183d 01h /pci/tags/rel_WB_B3/bench
34 Added missing include statements mihad 8197d 23h /pci/tags/rel_WB_B3/bench
33 Added some testcases, removed un-needed fifo signals mihad 8198d 20h /pci/tags/rel_WB_B3/bench
26 Modified testbench and fixed some bugs mihad 8212d 16h /pci/tags/rel_WB_B3/bench
19 *** empty log message *** mihad 8230d 17h /pci/tags/rel_WB_B3/bench
15 Initial testbench import. Still under development mihad 8230d 19h /pci/tags/rel_WB_B3/bench
3 New project directory structure mihad 8352d 16h /pci/tags/rel_WB_B3/bench

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