OpenCores
URL https://opencores.org/ocsvn/pci/pci/trunk

Subversion Repositories pci

[/] [pci/] [tags/] [rel_WB_B3] - Rev 67

Rev

Go to most recent revision | Details | Compare with Previous | Blame

Filtering Options

Clear current filter

Rev Log message Author Age Path
67 Changed BIST signals for RAMs. tadejm 7967d 11h /pci/tags/rel_WB_B3
66 Changed empty status generation in pciw_fifo_control.v mihad 7970d 21h /pci/tags/rel_WB_B3
65 Cleaned up non-blocking assignments in combinatinal logic statements mihad 7973d 19h /pci/tags/rel_WB_B3
64 The testcase I just added in previous revision repaired mihad 7973d 21h /pci/tags/rel_WB_B3
63 Added additional testcase and changed rst name in BIST to trst mihad 7973d 23h /pci/tags/rel_WB_B3
62 Added BIST signals for RAMs. mihad 7976d 16h /pci/tags/rel_WB_B3
60 Added support for Virtual Silicon two port RAM. Didn't run regression on it yet! mihad 7984d 16h /pci/tags/rel_WB_B3
59 Added meta flop module for easier meta stable FF identification during synthesis mihad 7984d 17h /pci/tags/rel_WB_B3
58 Removed all logic from asynchronous reset network mihad 7989d 18h /pci/tags/rel_WB_B3
57 Added completion expiration test for WB Slave unit. Changed expiration signalling mihad 7990d 00h /pci/tags/rel_WB_B3
56 Number of state bits define was removed mihad 7990d 14h /pci/tags/rel_WB_B3
55 Changed state machine encoding to true one-hot mihad 7990d 15h /pci/tags/rel_WB_B3
54 Changed Tsetup and Thold for WISHBONE models, due to difficulties encountered during gate level sim mihad 8023d 17h /pci/tags/rel_WB_B3
53 Updated for synthesis purposes. Gate level simulation was failing in some configurations mihad 8023d 20h /pci/tags/rel_WB_B3
52 Oops, never before noticed that OC header is missing mihad 8024d 00h /pci/tags/rel_WB_B3
51 Fixed a bug and provided testcase for it. Target was responding to configuration cycle type 1 transactions. mihad 8024d 00h /pci/tags/rel_WB_B3
50 Got rid of undef directives mihad 8026d 17h /pci/tags/rel_WB_B3
49 Extracted distributed RAM module from wb/pci_tpram.v to its own file, got rid of undef directives mihad 8026d 17h /pci/tags/rel_WB_B3
48 Extracted distributed RAM module from wb/pci_tpram.v to its own file mihad 8026d 17h /pci/tags/rel_WB_B3
47 Known issues repaired mihad 8026d 22h /pci/tags/rel_WB_B3

1 2 Next >

Show All

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.