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[/] [pci/] [tags/] [rel_WB_B3] - Rev 68

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Rev Log message Author Age Path
68 Changed wrong signal name scanb_sen into scanb_en. tadejm 7966d 08h /pci/tags/rel_WB_B3
67 Changed BIST signals for RAMs. tadejm 7966d 12h /pci/tags/rel_WB_B3
66 Changed empty status generation in pciw_fifo_control.v mihad 7969d 23h /pci/tags/rel_WB_B3
65 Cleaned up non-blocking assignments in combinatinal logic statements mihad 7972d 21h /pci/tags/rel_WB_B3
64 The testcase I just added in previous revision repaired mihad 7972d 23h /pci/tags/rel_WB_B3
63 Added additional testcase and changed rst name in BIST to trst mihad 7973d 01h /pci/tags/rel_WB_B3
62 Added BIST signals for RAMs. mihad 7975d 18h /pci/tags/rel_WB_B3
60 Added support for Virtual Silicon two port RAM. Didn't run regression on it yet! mihad 7983d 18h /pci/tags/rel_WB_B3
59 Added meta flop module for easier meta stable FF identification during synthesis mihad 7983d 19h /pci/tags/rel_WB_B3
58 Removed all logic from asynchronous reset network mihad 7988d 19h /pci/tags/rel_WB_B3
57 Added completion expiration test for WB Slave unit. Changed expiration signalling mihad 7989d 01h /pci/tags/rel_WB_B3
56 Number of state bits define was removed mihad 7989d 16h /pci/tags/rel_WB_B3
55 Changed state machine encoding to true one-hot mihad 7989d 17h /pci/tags/rel_WB_B3
54 Changed Tsetup and Thold for WISHBONE models, due to difficulties encountered during gate level sim mihad 8022d 18h /pci/tags/rel_WB_B3
53 Updated for synthesis purposes. Gate level simulation was failing in some configurations mihad 8022d 22h /pci/tags/rel_WB_B3
52 Oops, never before noticed that OC header is missing mihad 8023d 02h /pci/tags/rel_WB_B3
51 Fixed a bug and provided testcase for it. Target was responding to configuration cycle type 1 transactions. mihad 8023d 02h /pci/tags/rel_WB_B3
50 Got rid of undef directives mihad 8025d 18h /pci/tags/rel_WB_B3
49 Extracted distributed RAM module from wb/pci_tpram.v to its own file, got rid of undef directives mihad 8025d 18h /pci/tags/rel_WB_B3
48 Extracted distributed RAM module from wb/pci_tpram.v to its own file mihad 8025d 18h /pci/tags/rel_WB_B3

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