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[/] [pci/] [tags/] [rel_WB_B3] - Rev 98

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Rev Log message Author Age Path
98 Cleanup. mihad 7688d 17h /pci/tags/rel_WB_B3
97 Doing a little bit of cleanup. mihad 7688d 17h /pci/tags/rel_WB_B3
96 Update! mihad 7688d 17h /pci/tags/rel_WB_B3
95 Removed this file, because it was too large - long download time. mihad 7688d 17h /pci/tags/rel_WB_B3
94 Changed one critical PCI bus signal logic. mihad 7688d 17h /pci/tags/rel_WB_B3
93 Added a test application! mihad 7689d 00h /pci/tags/rel_WB_B3
92 Update! mihad 7689d 01h /pci/tags/rel_WB_B3
91 WebPack 5.2 constraint file for PCI CRT application was contributed by Uwe Bonnes (bon@elektron.ikp.physik.tu-darmstadt.de) tadejm 7724d 15h /pci/tags/rel_WB_B3
90 WebPack 5.2 project file for PCI CRT application was contributed by Uwe Bonnes (bon@elektron.ikp.physik.tu-darmstadt.de) tadejm 7724d 15h /pci/tags/rel_WB_B3
89 Burst 2 error fixed. mihad 7760d 15h /pci/tags/rel_WB_B3
88 Added the reset value parameter to the synchronizer flop module.
Added resets to all synchronizer flop instances.
Repaired initial sync value in fifos.		 mihad 7766d 14h /pci/tags/rel_WB_B3
87 Updated acording to RTL changes. mihad 7778d 12h /pci/tags/rel_WB_B3
86 Entered the option to disable no response counter in wb master. mihad 7778d 12h /pci/tags/rel_WB_B3
85 Changed Vendor ID defines. mihad 7778d 16h /pci/tags/rel_WB_B3
84 Changed vendor ID. mihad 7782d 10h /pci/tags/rel_WB_B3
83 Cleaned up the code. No functional changes. mihad 7807d 09h /pci/tags/rel_WB_B3
81 Updated synchronization in top level fifo modules. mihad 7821d 05h /pci/tags/rel_WB_B3
79 Updated. mihad 7824d 10h /pci/tags/rel_WB_B3
78 Old files with wrong names removed. mihad 7824d 11h /pci/tags/rel_WB_B3
77 Changed module and file names. Updated scripts accordingly. FIFO synchronizations changed. mihad 7824d 11h /pci/tags/rel_WB_B3

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