URL https://opencores.org/ocsvn/pcie_ds_dma/pcie_ds_dma/trunk

Subversion Repositories pcie_ds_dma

[/] [pcie_ds_dma/] [trunk/] [core/] [ds_dma64/] [pcie_src/] [components/] [pcie_core] - Rev 47

Rev	Log message	Author	Age	Path
47	Add files to ac701_a200t_core. No simulated.	dsmv	3775d 02h	/pcie_ds_dma/trunk/core/ds_dma64/pcie_src/components/pcie_core
46	work on the project ac701_a200t_core	dsmv	3776d 03h	/pcie_ds_dma/trunk/core/ds_dma64/pcie_src/components/pcie_core
40	set wb_clk to 32 MHz	dsmv	3975d 03h	/pcie_ds_dma/trunk/core/ds_dma64/pcie_src/components/pcie_core
38	sp605_lx45t_wishbone - correct reset, block_test_check, block_test_generate	dsmv	3982d 02h	/pcie_ds_dma/trunk/core/ds_dma64/pcie_src/components/pcie_core
32	Set 125 MHz for wishbone bus. Data transfered from TEST_GEN to computer without errors.	dsmv	4007d 01h	/pcie_ds_dma/trunk/core/ds_dma64/pcie_src/components/pcie_core
18	read block_id - ok	dsmv	4056d 23h	/pcie_ds_dma/trunk/core/ds_dma64/pcie_src/components/pcie_core
17	ambpex5_sx50t_wishbone - simulation is ok	dsmv	4078d 02h	/pcie_ds_dma/trunk/core/ds_dma64/pcie_src/components/pcie_core
2	add files from project DS_DMA on ds-dev.ru	dsmv	4330d 11h	/pcie_ds_dma/trunk/core/ds_dma64/pcie_src/components/pcie_core