URL https://opencores.org/ocsvn/pcie_ds_dma/pcie_ds_dma/trunk

Subversion Repositories pcie_ds_dma

[/] [pcie_ds_dma/] [trunk/] [core] - Rev 53

Rev	Log message	Author	Age	Path
53	fixes #67 - correction ctrl_ram_cmd.vhd for Spartan6 (is_dsp48=0)	dsmv	3123d 18h	/pcie_ds_dma/trunk/core
50	ac701_a200t_core - correct	dsmv	3300d 00h	/pcie_ds_dma/trunk/core
49	Обновление IP Core - ISE 14.7	dsmv	3844d 03h	/pcie_ds_dma/trunk/core
48	Обновление IP Core	dsmv	3850d 05h	/pcie_ds_dma/trunk/core
47	Add files to ac701_a200t_core. No simulated.	dsmv	3871d 22h	/pcie_ds_dma/trunk/core
46	work on the project ac701_a200t_core	dsmv	3872d 22h	/pcie_ds_dma/trunk/core
42	add coregen_s6 - components for Spartan 6	dsmv	4065d 23h	/pcie_ds_dma/trunk/core
40	set wb_clk to 32 MHz	dsmv	4071d 23h	/pcie_ds_dma/trunk/core
38	sp605_lx45t_wishbone - correct reset, block_test_check, block_test_generate	dsmv	4078d 21h	/pcie_ds_dma/trunk/core
32	Set 125 MHz for wishbone bus. Data transfered from TEST_GEN to computer without errors.	dsmv	4103d 21h	/pcie_ds_dma/trunk/core
29	Correct dmar, rst for wb_test; Add STATUS register.	dsmv	4111d 00h	/pcie_ds_dma/trunk/core
22	correct wishbone_test_en.htm	dsmv	4153d 01h	/pcie_ds_dma/trunk/core
18	read block_id - ok	dsmv	4153d 19h	/pcie_ds_dma/trunk/core
17	ambpex5_sx50t_wishbone - simulation is ok	dsmv	4174d 21h	/pcie_ds_dma/trunk/core
13	correct wishbone_test_en.htm	dsmv	4180d 23h	/pcie_ds_dma/trunk/core
12	Add description of project wishbone	dsmv	4180d 23h	/pcie_ds_dma/trunk/core
11	fixed cpl_byte_count in core64_tx_engine_m4.vhd	dsmv	4183d 02h	/pcie_ds_dma/trunk/core
2	add files from project DS_DMA on ds-dev.ru	dsmv	4427d 07h	/pcie_ds_dma/trunk/core