URL https://opencores.org/ocsvn/pdp1/pdp1/trunk

Subversion Repositories pdp1

[/] [pdp1/] [trunk/] [rtl/] [verilog] - Rev 7

Rev	Log message	Author	Age	Path
7	Typo fix.	yannv	2766d 15h	/pdp1/trunk/rtl/verilog
6	Modified to use dual-port RAM for scanline buffers, instead of one RAM per scanline. Note that XST fails to create dual-port RAM if write data on one port is constant! Next step is to use generic_dpram from opencores common.	yannv	4994d 18h	/pdp1/trunk/rtl/verilog
5	Add _i and _o suffixes to ports.	yannv	4994d 20h	/pdp1/trunk/rtl/verilog
4	Filled in some comments in vector2scanline.v. My very first Verilog module, bear with me.	yannv	5007d 14h	/pdp1/trunk/rtl/verilog
3	Unpacked source code for further development in svn.	yannv	5007d 15h	/pdp1/trunk/rtl/verilog