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[/] [pit/] [trunk/] [bench/] [sys_verilog/] [wb_master_model.sv] - Rev 24

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24 Added System Verilog Wishbone interface to module and testbench. rehayes 4755d 22h /pit/trunk/bench/sys_verilog/wb_master_model.sv
23 Simple language upgrade, will make bigger changes to add more system verilog features later. rehayes 4841d 09h /pit/trunk/bench/sys_verilog/wb_master_model.sv

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