URL https://opencores.org/ocsvn/pit/pit/trunk

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[/] [pit/] [trunk/] [rtl/] [verilog/] [pit_wb_bus.v] - Rev 18

Rev	Log message	Author	Age	Path
18	Traded 16 data registers for 3 address registers when wait states are enabled.	rehayes	5227d 18h	/pit/trunk/rtl/verilog/pit_wb_bus.v
17	Change WISHBONE ack signal so no output is generated when wait states are enabled and the bus transaction is terminated in the first cycle.	rehayes	5241d 14h	/pit/trunk/rtl/verilog/pit_wb_bus.v
14	Cosmetic update, changed no-blocking assigment to blocking assigment	rehayes	5449d 15h	/pit/trunk/rtl/verilog/pit_wb_bus.v
12	Fixed for single cycle reads	rehayes	5480d 14h	/pit/trunk/rtl/verilog/pit_wb_bus.v
10	Added SINGLE_CYCLE parameter for WISHBONE bus cycles	rehayes	5481d 17h	/pit/trunk/rtl/verilog/pit_wb_bus.v
9	fix problem with wb_wacc signal. Old method allowed data to be clocked into register twice.	rehayes	5487d 10h	/pit/trunk/rtl/verilog/pit_wb_bus.v
2	Initial Release March 14, 2009 - Bob Hayes	rehayes	5529d 14h	/pit/trunk/rtl/verilog/pit_wb_bus.v