URL https://opencores.org/ocsvn/pit/pit/trunk

Subversion Repositories pit

[/] [pit/] [trunk/] [rtl/] [verilog] - Rev 21

Rev	Log message	Author	Age	Path
21	Simple language upgrade	rehayes	4735d 13h	/pit/trunk/rtl/verilog
18	Traded 16 data registers for 3 address registers when wait states are enabled.	rehayes	5270d 18h	/pit/trunk/rtl/verilog
17	Change WISHBONE ack signal so no output is generated when wait states are enabled and the bus transaction is terminated in the first cycle.	rehayes	5284d 14h	/pit/trunk/rtl/verilog
14	Cosmetic update, changed no-blocking assigment to blocking assigment	rehayes	5492d 16h	/pit/trunk/rtl/verilog
12	Fixed for single cycle reads	rehayes	5523d 15h	/pit/trunk/rtl/verilog
10	Added SINGLE_CYCLE parameter for WISHBONE bus cycles	rehayes	5524d 18h	/pit/trunk/rtl/verilog
9	fix problem with wb_wacc signal. Old method allowed data to be clocked into register twice.	rehayes	5530d 11h	/pit/trunk/rtl/verilog
2	Initial Release March 14, 2009 - Bob Hayes	rehayes	5572d 14h	/pit/trunk/rtl/verilog