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[/] [plasma/] [tags/] [V3_0/] [vhdl/] [mlite_cpu.vhd] - Rev 352

Rev	Log message	Author	Age	Path
352		linus	5597d 05h	/plasma/tags/V3_0/vhdl/mlite_cpu.vhd
350		root	5626d 01h	/plasma/tags/V3_0/vhdl/mlite_cpu.vhd
140	This commit was manufactured by cvs2svn to create tag 'V3_0'.		6726d 13h	/plasma/tags/V3_0/vhdl/mlite_cpu.vhd
139	Major changes -- updated to Plasma Version 3	rhoads	6726d 13h	/plasma/tags/V3_0/vhdl/mlite_cpu.vhd
132	Changed "GENERIC" string to "DEFAULT" to be Xilinx friendly.	rhoads	7206d 12h	/plasma/tags/V3_0/vhdl/mlite_cpu.vhd
128	Reset all registers, constants now upper case.	rhoads	7343d 23h	/plasma/tags/V3_0/vhdl/mlite_cpu.vhd
124	Holger Lohn's fix for interrupts when 3-state pipeline enabled.	rhoads	7362d 12h	/plasma/tags/V3_0/vhdl/mlite_cpu.vhd
120	Make generics "GENERIC"	rhoads	7505d 02h	/plasma/tags/V3_0/vhdl/mlite_cpu.vhd
114	Matthias Grunewald's changes to get synthesis to work with Synopsys' FPGA Compiler II.	rhoads	7543d 13h	/plasma/tags/V3_0/vhdl/mlite_cpu.vhd
96	Simplify take_branch	rhoads	8066d 16h	/plasma/tags/V3_0/vhdl/mlite_cpu.vhd
83	Updated comments, accurate_timing on by default	rhoads	8068d 10h	/plasma/tags/V3_0/vhdl/mlite_cpu.vhd
73	pipeline, better reset	rhoads	8076d 11h	/plasma/tags/V3_0/vhdl/mlite_cpu.vhd
60	reset control	rhoads	8084d 16h	/plasma/tags/V3_0/vhdl/mlite_cpu.vhd
47	Altera	rhoads	8102d 13h	/plasma/tags/V3_0/vhdl/mlite_cpu.vhd
43	Renamed M-lite to Plasma	rhoads	8182d 13h	/plasma/tags/V3_0/vhdl/mlite_cpu.vhd
39	Changed name to M-lite to avoid trademark issues.	rhoads	8214d 18h	/plasma/tags/V3_0/vhdl/mlite_cpu.vhd