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[/] [plasma/] [tags/] [V3_0/] [vhdl] - Rev 106

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Rev Log message Author Age Path
106 better test mem_pause rhoads 7820d 03h /plasma/tags/V3_0/vhdl
105 better test mem_pause rhoads 7820d 03h /plasma/tags/V3_0/vhdl
103 shorten similation times rhoads 7821d 02h /plasma/tags/V3_0/vhdl
102 permit testing mem_pause rhoads 7821d 02h /plasma/tags/V3_0/vhdl
101 Correctly freeze the pipeline when mem_pause = '1' rhoads 7821d 02h /plasma/tags/V3_0/vhdl
99 correct upper 32-bits for mult(-1,-1) rhoads 7963d 02h /plasma/tags/V3_0/vhdl
98 Fix size of GENERIC ram. rhoads 7968d 00h /plasma/tags/V3_0/vhdl
97 added documentation rhoads 8032d 06h /plasma/tags/V3_0/vhdl
96 Simplify take_branch rhoads 8066d 08h /plasma/tags/V3_0/vhdl
95 register mem_write and mem_byte_sel for speed calculations rhoads 8066d 08h /plasma/tags/V3_0/vhdl
93 make run now runs for 500 us rhoads 8068d 01h /plasma/tags/V3_0/vhdl
92 Updated rhoads 8068d 01h /plasma/tags/V3_0/vhdl
91 Removed unused alu_function_type entries rhoads 8068d 01h /plasma/tags/V3_0/vhdl
90 Now multiplies two bits at a time rhoads 8068d 01h /plasma/tags/V3_0/vhdl
89 Use address_reg instead of address_data to break timing slow down rhoads 8068d 01h /plasma/tags/V3_0/vhdl
88 Cleanup spaces rhoads 8068d 01h /plasma/tags/V3_0/vhdl
87 Seperated left and right shift variables rhoads 8068d 01h /plasma/tags/V3_0/vhdl
86 Updated comment rhoads 8068d 01h /plasma/tags/V3_0/vhdl
85 Use ADDRESS_WIDTH when decoding mem_sel rhoads 8068d 01h /plasma/tags/V3_0/vhdl
84 Fixed comment rhoads 8068d 01h /plasma/tags/V3_0/vhdl

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