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[/] [plasma/] [tags/] [V3_0/] [vhdl] - Rev 123

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123 Uncomment out the Altera portion. Xilinx users may need to re-comment out this section. rhoads 7428d 10h /plasma/tags/V3_0/vhdl
122 Added comment to explain why c_bus isn't delayed but reg_dest is delayed. rhoads 7492d 10h /plasma/tags/V3_0/vhdl
121 Added Matthias Gruenewald's tri-state area-optimized option rhoads 7503d 23h /plasma/tags/V3_0/vhdl
120 Make generics "GENERIC" rhoads 7503d 23h /plasma/tags/V3_0/vhdl
119 Opcodes from count.c rhoads 7542d 10h /plasma/tags/V3_0/vhdl
118 Merged Matthias Grunewald's changes to use tri-state for smaller Xilinx FPGA. rhoads 7542d 10h /plasma/tags/V3_0/vhdl
117 Part of Matthias Grunewald's changes to use tri-state for smaller Xilinx FPGA. rhoads 7542d 10h /plasma/tags/V3_0/vhdl
116 Matthias Grunewald's changes to use tri-state for smaller Xilinx FPGA. rhoads 7542d 10h /plasma/tags/V3_0/vhdl
115 Matthias Grunewald's changes for Xilinx FPGA dual-port RAM. rhoads 7542d 10h /plasma/tags/V3_0/vhdl
114 Matthias Grunewald's changes to get synthesis to work with Synopsys' FPGA Compiler II. rhoads 7542d 10h /plasma/tags/V3_0/vhdl
113 Matthias Grunewald's bug fixes:
Branch and compare instructions didn't interpret immediate as signed.
rhoads 7542d 10h /plasma/tags/V3_0/vhdl
112 Merged Matthias Grunewald's changes to use tri-state for smaller Xilinx FPGA. rhoads 7542d 10h /plasma/tags/V3_0/vhdl
108 changed interrupt vector from 0x30 to 0x3c rhoads 7816d 06h /plasma/tags/V3_0/vhdl
107 merged rising_edge(clk) statements rhoads 7816d 06h /plasma/tags/V3_0/vhdl
106 better test mem_pause rhoads 7819d 09h /plasma/tags/V3_0/vhdl
105 better test mem_pause rhoads 7819d 09h /plasma/tags/V3_0/vhdl
103 shorten similation times rhoads 7820d 08h /plasma/tags/V3_0/vhdl
102 permit testing mem_pause rhoads 7820d 08h /plasma/tags/V3_0/vhdl
101 Correctly freeze the pipeline when mem_pause = '1' rhoads 7820d 08h /plasma/tags/V3_0/vhdl
99 correct upper 32-bits for mult(-1,-1) rhoads 7962d 08h /plasma/tags/V3_0/vhdl

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